In recently developed merged memory logic (MML), a memory cell array such as dynamic random access memory (DRAM) and a logic array such as analog circuits or peripheral circuits are integrated in a single chip. With the advent of MML, multimedia functions have been greatly improved and, high-integration and high-speed operation of semiconductor devices have been more effectively achieved.
On the other hand, to achieve the high-speed operation of analog circuits, a capacitor with high capacitance is in development. Generally, in a capacitor having a polysilicon-insulator-polysilicon (PIP) structure, the interface between the dielectric and the upper/lower electrodes may be oxidized to form a natural oxide layer because the upper and lower electrodes are made of polysilicon. Such natural oxide layer may lower the total capacitance of the capacitor. In addition, the capacitance of the capacitor may be reduced due to depletion regions which are created in the polysilicon layer. Such a capacitor has a low capacitance and is unsuitable for devices requiring high-speed and high-frequency operation.
To obviate these problems, new capacitor structures such as metal-insulator-silicon (MIS) and metal-insulator-metal (MIM) have been suggested. The MIM capacitor is widely used in high performance semiconductor devices because it has low specific resistance and no parasitic capacitance due to depletion regions. Recently, technology for forming a metal interconnect of a semiconductor device by using copper with low specific resistance instead of aluminum has been introduced. Therefore, various MIM capacitors with copper electrodes are being suggested.
FIGS. 1a and 1b are cross-sectional views illustrating a conventional process of fabricating a MIM capacitor and a dual damascene structure interconnect of a semiconductor device. Referring to FIG. 1a, a lower insulating layer 10 is deposited on a semiconductor substrate 1. A first metal interconnect 15 and a second metal interconnect 20 are then formed in the lower insulating layer 10. After a metal layer is deposited over the resulting structure, a portion of the metal layer is removed to form a lower electrode 25 of a capacitor on the second metal interconnect 20. A dielectric layer 30 is then deposited over the semiconductor substrate 1 including over the lower capacitor electrode 25. After a second metal layer is deposited on the dielectric layer 30, a portion of the second metal layer is removed to form an upper electrode 35 of the capacitor on the lower electrode 25. Next, an interlayer dielectric (ILD) layer 40 is deposited over the resulting structure.
Referring to FIG. 1b, the ILD layer 40 is planarized by a chemical mechanical polish (CMP) process. Some portion of the ILD layer 40 and the dielectric layer 30 is then removed by using an etching process to form a via hole V1 through the ILD layer 40. The via hole V1 exposes a portion of the top surface of the first metal interconnect 15. Next, a first trench T1 is formed in the upper part of the via hole VI. A second trench T2 is formed through the ILD layer 40 on the upper electrode 35. The second trench T2 exposes a portion of the top surface of the upper electrode 35. The via hole V1, the first trench T1, and the second trench T2 are filled with copper and then planarized by a CMP process. As a result, a damascene structure interconnect 45 and a contact plug 50 are completed.
However, the above-described prior art process of fabricating an MIM capacitor and a dual damascene structure interconnect has several problems. First, the above-described process requires an additional metal interconnect process to form a metal interconnect to apply a bias to the lower electrode of the capacitor. In addition, the above-described process is rather complicated because the via hole and the trench on the upper electrode are formed by using separate unit processes.